Senior Engineer -VLSI
May 2012 — Present
Senior Engineer - VLSI having about 1 year and 7 months of work experience in System Verilog, VHDL and VMM. During this tenure, gained exposure in creating Verification Environments from scratch using VMM, SV and VHDL. This includes writing all the components like generator, driver, interface, monitor, scoreboard, protocol checker and test cases, and adding functional coverage.