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Aakash Chugh

Aakash Chugh

Product Engineer / Low Power Design Engineer

Cadence Design Systems

San Jose, CA - 95131

Product Engineer at Cadence Design Systems


Cadence Design Systems

Product Engineer

IEEE1801 - Power Intent Integration and Support
- Working on designs using IEEE1801 power spec for power intent specification.
- Familiar with CPF and UPF, and how to translate one to the other.
- Hands on experience in LP lint checks, Insertion, and Pre-Synthesis and Post-Synthesis Validation
Customer Support
- Assisting Broadcom with their tapeout by verifying their Low Power Design using Cadence Verification Tools
- Assisting Nvidia with conversion from UPF to CPF and setting up the Cadence flow
- Assisting Atmel by providing IEEE1801 support on verification tools
Tutorials and Rapid Adoption Kits
- Developed the low power ILM flow using CPF and Cadence synthesis tools
- Developed tutorials on how to set up the Low Power flow on Cadence Front End Tools and delivered them to Application Engineers
- Developed tutorials for conversion from IEEE1801/UPF to CPF and how to use the IEEE1801 flows in Cadence tools
- Migrated all tutorials to IEEE1801 format and helped perform product validation of Front End Tools

Career medium 02
Career medium 05


Summer Intern

- Coded in Verilog and synthesized the design of the digital section of the next generation MEMS microphone.
- Custom coded the I2C port, which was unique to the design
- Helped migrate the VHDL portion of the design to Verilog
- Performed timing, area and power analysis on the design


Carnegie Mellon University

Master of Science (MS), Electrical and Computer Engineering

Graduated with a 3.27 GPA.
Concentration in Low Power Design, VLSI, Digital Design, CAD, Digital System Testing and Verification.
Teaching Assistant for Signals and Systems, where primary responsibilities included creating Lab components, conducting the Labs, grading the labs and also grading exams.
Research Assistant for Dr Diana Marculescu, where a translator was developed for reading in text files which contained logic for biological networks and a verilog file was dumped out.

Education medium 05

Manipal Institute of Technology

Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

Graduated with a GPA of 9.35/10.00